Application specific integrated circuits (ASICs) routinely achieve densities of millions of gates per chip, which presents an especially difficult testing challenge. ASICs are typically designed by combining pre-defined, standard functional blocks called core cells from a variety of sources with discrete logic to perform a desired function or group of functions. Although standard test vectors or test strategies may be supplied with the core cells, their internal connections to one another inside the ASIC are frequently inaccessible from the pins of the ASIC, rendering the standard tests unusable and complicating the testing procedure.
A common technique used to gain access to core cells inside an ASIC is known as full-scan design, in which every flip-flop of a logic circuit has a multiplexer placed at its data input, so that when a test mode signal is applied to the control input of the multiplexers, all the flip-flops are chained together into a shift register or scan chain. The scan chain is formed by connecting Q from a flip-flop to the SI of the next flip-flop. The test mode signal/scan enable signal of the multiplexer determines which signal (SI or D) is captured in the flip-flop and made available at Q. A scan test is performed by clocking test patterns into the shift register and clocking out the test results.
Very large scale integrated (“VLSI”) circuits include scan chains for testing some or all parts of the integrated circuit. A scan chain typically includes a plurality of flip-flops that are shifted to set the integrated circuit in a given state and determine if each part of the integrated circuit operates correctly. However, scan chains are only effective if the scan chains themselves are operable and do not include defects. A defect in a scan chain can prevent proper testing of the integrated circuit as it may prevent a circuit from being set in a given state.